mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 48

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

CPM
Table 36
Figure 30
48
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDA/SCL rise time
SDA/SCL fall time
Stop condition setup time
Notes:
1.F
2.divider = f
MAX
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then
In master mode: divider = BRGCLK/(f
In slave mode: divider = BRGCLK/(f
SDA
disabled and 18 if enabled.
FMAX=BRGCLK/48
FMAX=BRGCLK/576
SCL
shows CPM I
is a a diagram of CPM I
= BRGCLK/(min_divider*prescaler). Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter
SCL
t
SCHDL
Characteristic
/prescaler.
2
2
t
SDHDL
t
2
SDLCL
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
C AC Timing.
2
2
t
SCLCH
Figure 30. CPM I
2
C Bus Timing.
SCL
Table 36. CPM I
SCL
*prescaler)
*prescaler) = 2*(I2BRG[DIV]+3)
t
SCLDX
Symbol
t
t
t
t
t
t
t
t
t
t
SDVCH
SCHDH
SDHDL
SCLCH
SCHCL
SCHDL
SCLDX
SDLCL
SRISE
SFALL
f
f
SCL
SCL
t
SRISE
2
C Bus Timing Diagram
t
2
SCHCL
C AC Timing
BRGCLK/16512
2/(divider * f
3/(divider * f
2/(divider * f
3/(divider * f
2/(divider * f
1/(2.2 * f
1/(2.2 * f
1/(2.2 * f
t
SFALL
Min
—
—
0
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
)
)
)
)
)
)
)
)
BRGCLK/48
1/(10 * f
1/(33 * f
t
SDVCH
F
Max
MAX
—
—
—
—
—
—
—
—
SCL
SCL
1
t
Freescale Semiconductor
SCHDH
)
)
Unit
Hz
Hz
s
s
s
s
s
s
s
s
s
s