mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 37

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Local bus clock to output high impedance
for LAD/LDP
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
2.All timings are in reference to local bus clock for DLL bypass mode. Timings may be negative with respect to the local bus
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4.All signals are measured from OV
5.Input timings are measured at the pin.
6.The value of t
7.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
8.Guaranteed by characterization.
9.Guaranteed by design.
for inputs and t
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
case for clock one(1). Also, t
respect to the output (O) going invalid (X) or output hold time.
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes
LCLK by t
complementary signals at OV
in question for 3.3-V signaling levels.
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
through the component pin is less than or equal to the leakage current specification.
LBKHKT
LBOTOT
Parameter
Table 32. Local Bus General Timing Parameters—DLL Bypassed (continued)
(First two letters of functional block)(reference)(state)(signal)(state)
.
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
LBKHOX
DD
DD
/2.
/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OV
symbolizes local bus timing (LB) for the t
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
POR Configuration
(default)
(default)
(default)
(default)
(default)
(default)
Symbol
t
(First two letters of functional block)(signal)(state) (reference)(state)
t
t
t
t
t
t
LBKHOV4
LBKLOV2
LBKLOV3
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
for outputs. For example, t
1
LBK
LBK
clock reference (K) goes high (H), in this
clock reference (K) to go high (H), with
Min
-3.2
-2.3
-3.2
-2.3
—
—
—
—
—
Max
-0.1
1.4
1.5
0.2
1.5
0.2
1.5
—
—
0
0
LBIXKH1
Unit
symbolizes local
ns
ns
ns
ns
ns
ns
ns
DD
of the signal
Local Bus
Notes
4
4
4
4
4
7
7
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