mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 81

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

15.2 Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in
There is no default for this PLL ratio; these signals must be pulled to the desired values.
15.3 e500 Core PLL Ratio
Table 58
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in
Freescale Semiconductor
describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
Binary Value of LA[28:31] Signals
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Binary Value of LALE, LGPL2 Signals
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 58. e500 Core to CCB Ratio
Table
Table 57. CCB Clock Ratio
00
01
10
11
57.
16:1 ratio CCB clock: SYSCLK (PCI bus)
10:1 ratio CCB clock: SYSCLK (PCI bus)
12:1 ratio CCB clock: SYSCLK (PCI bus)
2:1 ratio CCB clock: SYSCLK (PCI bus)
3:1 ratio CCB clock: SYSCLK (PCI bus)
4:1 ratio CCB clock: SYSCLK (PCI bus)
5:1 ratio CCB clock: SYSCLK (PCI bus)
6:1 ratio CCB clock: SYSCLK (PCI bus)
8:1 ratio CCB clock: SYSCLK (PCI bus)
9:1 ratio CCB clock: SYSCLK (PCI bus)
Ratio Description
2:1 e500 core:CCB
5:2 e500 core:CCB
3:1 e500 core:CCB
7:2 e500 core:CCB
Ratio Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table
58.
Clocking
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