mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 33

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

7.3.2 MII Management AC Electrical Specifications
Table 29
Freescale Semiconductor
At recommended operating conditions with OV
Input high current (OV
Input low current (OV
Note:
1.Note that the symbol V
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
2.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the maximum frequency is
3.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
4.Guaranteed by design.
(reference)(state)
symbolizes management data timing (MD) for the time t
invalid (X) or data hold time. Also, t
input signals (D) reach the valid state (V) relative to the t
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
8.3 MHz and the minimum frequency is 1.2 MHz; for a CCB clock of 333 MHz, the maximum frequency is 10.4 MHz
and the minimum frequency is 1.5 MHz).
CCB clock of 333 MHz, the delay is 48 ns).
Parameter/Condition
provides the MII management AC timing specifications.
Parameter
for inputs and t
Table 28. MII Management DC Electrical Characteristics (continued)
DD
DD
= Max, V
IN
= Max, V
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
, in this case, represents the OV
Table 29. MII Management AC Timing Specifications
IN
(first two letters of functional block)(reference)(state)(signal)(state)
IN
= 0.5 V)
1
= 2.1 V)
DD
MDDVKH
Symbol
t
t
t
t
MDKHDX
MDDXKH
is 3.3 V ± 5%.
MDKHDV
MDDVKH
t
t
t
MDCH
MDCR
f
t
MDHF
MDC
MDC
symbolizes management data timing (MD) with respect to the time data
1
Symbol
0.893
I
I
Min
IH
IN
IL
96
32
10
—
—
MDC
5
0
MDC
symbol referenced in
from clock reference (K) high (H) until data outputs (D) are
clock reference (K) going to the high (H) state or setup
(first two letters of functional block)(signal)(state)
Typ
—
—
—
—
—
—
—
—
–600
Min
—
Table 1
2*[1/(f
2*[1/(f
Ethernet: Three-Speed, MII Management
for outputs. For example, t
1120
Max
10.4
ccb_clk
ccb_clk
and
10
10
—
—
—
Max
40
—
Table
/8)]
/8)]
2.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
μA
μA
MDKHDX
Notes
2, 4
3
3
4
4
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