mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 60

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
The following conditions apply when in manual mode:
5.3.6 Programming the PLL
The following procedure shows how to program the PLL.
60
1. Choose the desired bus frequency, f
2. Choose a practical PLL reference frequency, f
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ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time, t
Acquisition/Lock Time
control register (PCTL).
Software must wait a given time, t
clock source to CGMOUT (BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
solve for the other.
The relationship between f
the reference is 4MHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See
Specifications.
Choose the reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f
and R = 1. If f
practical choices of f
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
RCLK
R
cannot meet this requirement, use the following equation to solve for R with
RCLK
=
Specifications.), after turning on the PLL by setting PLLON in the PLL
round R
, and choose the f
BUS
MC68HC908JW32 Data Sheet, Rev. 5
and f
MAX
AL
, after entering tracking mode before selecting the PLL as the
×
VCLK
BUSDES
f
f
VCLK
⎧
⎨
⎩
VCLK
⎛
⎜
⎝
f
------------------------- -
VCLKDES
is governed by the equation:
f
RCLK
NOTE
=
=
RCLK
, or the desired VCO frequency, f
6
2
----------- f
RCLK
P
×
R
VCLK
N
that gives the lowest R.
⎞
⎟
⎠
f
BUS
(
–
, and the reference clock divider, R. Typically,
RCLK
, and the reference frequency, f
integer
RCLK
)
/R. For stability and lock time reduction,
RCLK
⎛
⎜
⎝
f
------------------------- -
VCLKDES
f
RCLK
to an integer divisor of f
Chapter 19 Electrical
RCLK
⎞
⎟
⎠
⎫
⎬
⎭
to a value determined
ACQ
Freescale Semiconductor
VCLKDES
(See
RCLK
5.8
; and then
BUSDES
, is
,