mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 155

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

SUSPND — SUSPEND Detection Flag
11.5.3 USB Status Interrupt Mask Register (USIMR)
EP0_STALL — Forced EP0 STALL Handshake Enable
SETUPIE — SETUP Request Interrupt Mask
SOFIE — Start-of-frame Interrupt Mask
CONFIG_CHGIE — Configuration Change Interrupt Mask
Freescale Semiconductor
This read/write bit is set when the module detects a suspend state on the USB bus or the bus is idle
for 3ms. The module will enter suspend mode when this bit is set. In order to reduce the power
consumption, user is recommended to stop the USB module clock by clearing the USBCLKEN bit in
USBCR register before putting the MCU in STOP mode. Writing zero to clear the bit. Writing one to
the bit has no effect. Reset clears this bit.
This write only bit is used to provide protocol STALL to the control endpoint. Writing one to the bit
causes endpoint 0 to return STALL in response to any IN or OUT token issue by the USB host until the
next SETUP transaction. The bit can only be erased by module hardware, writing zero to the bit has
no effect. Reset also clears this bit.
This read/write bit enables a CPU interrupt request when GET_DESCRIPTOR, SYNC_FRAME or
class/vendor specific request is received or SETUP flag of USB status register (USBSR) is set. Reset
clears this bit.
This read/write bit enables a CPU interrupt request when a start-of-frame signal is detected on the USB
bus or SOF flag of USB status register (USBSR) is set. Reset clears this bit.
This read/write bit enables a CPU interrupt request when a configuration change from zero to one is
detected or CONFIG_CHG flag of USB status register (USBSR) is set. Reset clears this bit.
1 = SUSPEND state is detected
0 = No suspend state is detected
1 = Send STALL handshake
0 = Do not response STALL handshaking
1 = CPU interrupt is enabled when SETUP flag in USBSR is set
0 = CPU interrupt is disabled when SETUP flag in USBSR is set
1 = SOF interrupt is enabled
0 = SOF interrupt is disabled
1 = CPU interrupt is enabled when CONFIG_CHG flag in USBSR is set
0 = CPU interrupt is disabled when CONFIG_CHG flag in USBSR is set
Address:
Reset:
Read:
Write:
$0053
Bit 7
R
R
0
Figure 11-5. USB Status Interrupt Mask Register
= Reserved
EP0_STALL
6
0
0
MC68HC908JW32 Data Sheet, Rev. 5
SETUPIE
5
0
SOFIE
4
0
CONFIG_
CHGIE
3
0
USBRE-
SETIE
2
0
RESUME-
FIE
1
0
USB Module Registers
SUSP-
NDIE
Bit 0
0
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