mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 126

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface Module (SPI)
10.4 Functional Description
Figure 10-2
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
The following paragraphs describe the operation of the SPI module.
10.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. (See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
126
$004C SPI Control Register (SPCR)
$004D
$004E
Addr.
10.13.2 SPI Status and Control
SPI Status and Control
Register Name
shows the structure of the SPI module.
SPI Data Register
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See
(SPSCR)
Register
(SPDR)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 10-1. SPI I/O Register Summary
SPRIE
SPRF
Bit 7
MC68HC908JW32 Data Sheet, Rev. 5
R7
T7
0
0
Register.) Through the SPSCK pin, the baud rate generator of the
= Unimplemented
ERRIE
R6
T6
R
Figure
6
0
0
NOTE
SPMSTR
10-3.)
OVRF
10.13.1 SPI Control
R5
T5
5
1
0
MODF
CPOL
Unaffected by reset
R4
T4
4
0
0
CPHA
SPTE
R3
T3
R
3
1
1
Register.)
= Reserved
MODFEN
SPWOM
R2
T2
2
0
0
Freescale Semiconductor
SPR1
SPE
R1
T1
1
0
0
SPTIE
SPR0
Bit 0
R0
T0
0
0