mc68hc908jw32 Freescale Semiconductor, Inc, mc68hc908jw32 Datasheet - Page 58

• Manufacturer Part Number: mc68hc908jw32
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
5.3.3 PLL Circuits
The PLL consists of these circuits:
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGMXFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
(L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
external high-frequency clock source, use R to divide the external frequency to between 1MHz and
8MHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
pre-scaler divider and a programmable modulo divider. The pre-scaler divides the VCO clock by a
power-of-two factor P (the CGMPCLK) and the modulo divider reduces the VCO clock by a factor, N. The
dividers’ output is the VCO feedback clock, CGMVDV, running at a frequency, f
5.3.6 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in
reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, f
this comparison.
58
RCLK
RDV
•
•
•
•
•
•
•
= f
, and is fed to the PLL through a programmable modulo reference divider, which divides f
E
Voltage-controlled oscillator (VCO)
Reference divider
Frequency pre-scaler
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
)f
RCLK
NOM
.
/R. With an external crystal (4MHz), always set R = 1 for specified performance. With an
RDV
5.3.4 Acquisition and Tracking
. The circuit determines the mode of the PLL and the lock condition based on
NOM
for more information.)
, (125 kHz) times a linear factor, L, and a power-of-two factor, E, or
MC68HC908JW32 Data Sheet, Rev. 5
Modes. The value of the external capacitor and the
VCLK
VRS
. Modulating the voltage on the
, is fed back through a programmable
VRS
is equal to the nominal
VDV
= f
Freescale Semiconductor
VCLK
/(N × 2
RCLK
P
). (See
by a