mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 248

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mc68hc908jb8

Manufacturer Part Number
mc68hc908jb8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
17.4.2 CPU During Break Interrupts
17.4.3 TIM During Break Interrupts
17.4.4 COP During Break Interrupts
17.5 Low-Power Modes
17.5.1 Wait Mode
Technical Data
248
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops the timer counter.
The COP is disabled during a break interrupt when V
on the RST pin.
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see
0 to it.
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
8.7 Low-Power
Break Module (BREAK)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Modes). Clear the SBSW bit by writing logic
Freescale Semiconductor
REG
+ V
HI
is present

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