mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 169

• Manufacturer Part Number: mc68hc908jb8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.4.2 Baud Rate
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Table 10-2
and monitor mode.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
The communication baud rate is dependant on oscillator frequency,
f
is by IRQ = V
the PTA3 pin is at logic zero upon entry into monitor mode, the divide by
ratio is 312.
XCLK
Monitor
Modes
User
Notes:
1. If the high voltage (V
Blank reset vector,
IRQ = V
Monitor Mode
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
. The state of PTA3 also affects baud rate if entry to monitor mode
IRQ = V
Entry By:
DD
Disabled
Enabled
is a summary of the vector differences between user mode
Table 10-2. Monitor Mode Vector Differences
DD
COP
+ V
DD
Table 10-3. Monitor Baud Rate Selection
Monitor ROM (MON)
HI
+ V
(1)
HI
DD
Vector
$FEFE
$FFFE
. When PTA3 is high, the divide by ratio is 625. If
Reset
High
Oscillator Clock
Frequency, f
+ V
HI
) is removed from the IRQ pin or the RST pin, the SIM
3 MHz
6 MHz
3 MHz
6 MHz
3 MHz
Vector
$FEFF
$FFFF
Reset
Low
CLK
Functions
$FEFC
Vector
$FFFC
Break
High
PTA3
X
X
0
1
1
$FEFD
Vector
$FFFD
Break
Low
Functional Description
Monitor ROM (MON)
Baud Rate
$FEFC
9600 bps
9600 bps
4800 bps
9600 bps
4800 bps
Vector
$FFFC
High
SWI
Technical Data
$FEFD
Vector
$FFFD
Low
SWI
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