mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 239

• Manufacturer Part Number: mc68hc908jb8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.4 I/O Signals
15.4.1 OSCXCLK
15.4.2 STOP Instruction
15.4.3 COPCTL Write
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V
the COP.
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
OSCXCLK is the clock doubler output signal. OSCXCLK frequency is
double of the crystal frequency.
The STOP instruction clears the COP prescaler.
Writing any value to the COP control register (COPCTL) (see
Control
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
DD
+ V
Computer Operating Properly (COP)
Register) clears the COP counter and clears bits 12 through 5
HI
. During the break state, V
DD
Computer Operating Properly (COP)
+ V
HI
on the RST pin disables
Figure
Technical Data
15.5 COP
I/O Signals
15-1.
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