mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 106

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mc68hc908jb8

Manufacturer Part Number
mc68hc908jb8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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System Integration Module (SIM)
Technical Data
106
INTERRUPT
INTERRUPT
MODULE
MODULE
I BIT
I BIT
R/W
R/W
IAB
IDB
IAB
IDB
DUMMY
DUMMY
Interrupts are latched and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
8-10
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
shows interrupt recovery timing.
CCR
Figure 8-10. Interrupt Recovery
SP – 3
SP – 1
Figure 8-9. Interrupt Entry
System Integration Module (SIM)
A
SP – 2
SP – 2
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
X
X
Figure 8-9
SP – 3
SP – 1
PC –1 [15:8] PC – 1[7:0]
A
SP – 4
SP
shows interrupt entry timing.
CCR
VECT H
PC
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
Freescale Semiconductor
START ADDR
OPCODE
Figure

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