mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 244

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mc68hc908jb8

Manufacturer Part Number
mc68hc908jb8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Low Voltage Inhibit (LVI)
16.4 LVI Control Register (CONFIG)
16.5 Low-Power Modes
16.5.1 Wait Mode
16.5.2 Stop Mode
Technical Data
244
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
Address:
LVID —þLow Voltage Inhibit Disable Bit
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
The LVI module, when enabled, will continue to operate in WAIT Mode.
The LVI module, when enabled, will continue to operate in STOP Mode.
Reset:
Read:
Write:
DETECTOR
LOW V
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
V
DD
$001F
Bit 7
DD
0
0
Figure 16-2. Configuration Register (CONFIG)
Low Voltage Inhibit (LVI)
V
V
Figure 16-1. LVI Module Block Diagram
= Unimplemented
DD
DD
> V
< V
6
0
0
LVR
LVR
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
= 0
= 1
URSTD
5
0
LVID
4
0
SSREC
3
0
LVID
COPRS
Freescale Semiconductor
2
0
STOP
1
0
LVI RESET
COPD
Bit 0
0

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