dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 87

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

PLL USAGE CONSIDERATIONS
MOTOROLA
The PLL can be used to generate the DSP core system clock. The specific operating
frequency is determined by choosing the appropriate input frequency (EXTAL) and
the ID, YD, and PD counter divider ratios. These ratios are defined in the PLL Control
Register 0 (PCR0), using the following formula:
The best PLL performance is attained when the ID and YD counter values are kept in
a small range to minimize lock time and jitter. A higher input frequency to the PLL
will result in a higher correction rate, therefore producing a more stable output clock.
For example, with an input EXTAL frequency of 10 MHz, a PLCR0 value of $0317 will
result in a more stable 60 MHz system clock than will a PLCR0 value of $0F5F. A
programming ratio of EXTAL/(ID + 1) 1 MHz is recommended.
The External Filter Capacitor (XFC) is another parameter affecting lock time and
stability of the PLL system. This low-leakage capacitor should be connected between
SXFC and GND
SXFC) should be isolated, as much as possible, from any external noise, preferably in
a separate ground plane. The PLL modifies the voltage on the VCO by varying the
charge on the capacitor connected to XFC. In effect, the PLL can be viewed as a
second-order control system in which the SFC influences the natural frequency and
damping factor for the system. If the capacitor is too small, the system will be
severely underdamped and unstable, which yields a large jitter. If the capacitor is too
large, the PLL becomes overdamped and may not be able to adjust to voltage changes
within a reasonable lock time. The PLL lock detection circuitry does not require the
system to be underdamped.
A recommended connection diagram is shown in Figure 4-7 on page 4-12.
S
, as close as possible to the pins. The PLL pins (VDDS, GNDS, and
Fosc
DSP56167/D, Rev. 1
=
------------------------------------ EXTAL
ID
YD
+
1
+
1
2
PD
PLL Usage Considerations
Design Considerations
4-11