dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 11

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

PLL AND CLOCK
ADDRESS BUS
MOTOROLA
EXTAL
CLKO
SXFC
A0–A15
Signal
Name
Names
Signal
Output
Signal
Input
Input
Type
Output
Signal
Type
during
driven
Reset
Input
Chip-
Input
State
Tri-stated Address Bus—These signals change in T0 and specify the
during
Reset
State
Table 1-4 PLL and Clock Signals
External Clock/Crystal Input—This input should be connected to
an external crystal or to an external oscillator. A sine wave with a
minimum swing of 1 V
squared, the input clock can provide the DSP core clock directly.
Internally, the clock is divided to produce a four-phase instruction
clock (T0, T1, T2, and T3) with the instruction clock period being
equal to two input clock periods. This input clock can also be
selected as the input clock for the on-chip codec and PLL.
PLL Output Clock—This buffered clock signal output can be one of
three signals, selected by programming the two bits, CS1 and CS2 in
the PLL Control Register (PLCR):
CLKO can be disabled by setting the Clockout Disable (CD) Bit 7 of
the Operating Mode Register (OMR).
Note:
External Filter Capacitor—Connect an external capacitor to the
filter circuit of the PLL between this input and V
of this document for additional information about capacitor size
selection.
Table 1-5 Address Bus Signals
address for external program and data memory accesses. If there
is no external bus activity, A0–A15 remain at their previous
values to reduce power consumption.
•
•
•
DSP56167/D, Rev. 1
A squared version of the EXTAL input
A squared version of the EXTAL input divided by 2
A delayed version of the DSP core master clock
For information about programming the PLCR or OMR, see
the
DSP56100 Family Manual
P
Signal Description
can be applied to this pin. After being
Signal Description
.
Signal/Pin Descriptions
DDS
. See
PLL and Clock
Section 2
1-5