dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 14

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal/Pin Descriptions
Bus Control
1-8
BR
Signal
Name
Output
Signal
Input
Type
or
Input
during
Reset
State
Table 1-7 Bus Control Signals (Continued)
Bus Request—After reset, this signal is an input (Slave mode).
When the BR input is asserted, an external device, such as another
processor or DMA controller, becomes the master of the external
address and data buses. The DSP asserts the BG output signal after
a few T states (i.e., T0, T1, etc.) to acknowledge the BR input. The
DSP releases control of the external bus at the earliest possible time
consistent with proper synchronization. At release, the DSP tri-
states PEREN, PS/DS, RD, WR, and R/W, and deasserts the BB
signal to indicate the bus is released. While the bus is released, the
DSP may continue internal operations using internal memory
spaces. If external access is required, the DSP bus controller inserts
WS until the bus is available. Bus control returns to the DSP when
the BR and BB inputs are both deasserted.
Note:
Note:
If the master bit in the Operating Mode Register (OMR) is set, this
signal is an output (Master mode). In this mode the DSP is not the
default bus master and must assert BR to gain control of the external
bus. After asserting BR, the DSP bus controller inserts WS until the
BG input is asserted. The DSP begins processing external accesses
on the rising edge of the clock after BB is sampled high. BR remains
asserted until the DSP no longer needs the bus. In Master mode, the
Request Hold (RH) bit in the BCR allows BR to be asserted under
software control.
Note:
Note:
DSP56167/D, Rev. 1
Interrupts are not serviced while a DSP instruction is
waiting for the bus.
BR cannot interrupt the execution of a read-modify-write
instruction.
During external accesses caused by an instruction executed
out of external program memory, BR remains asserted for
consecutive external X data memory accesses and continues
toggling for consecutive external program memory accesses
until RH in the BCR is set.
In Master mode, BR can also be used for non-arbitration
uses. If BG is always asserted, BR is asserted in T0 of every
external bus access. In this case, BR can act as a chip select
signal to enable and disable an external memory device
between external and internal accesses. In this case, the BR
timing is similar to A0–A15, R/W, and PS/DS and is
asserted and deasserted in T0.
Signal Description
MOTOROLA