dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 108

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dsp56167

Manufacturer Part Number
dsp56167
Description
Advance Information 16-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Design Considerations
Special Design Considerations for Conversions from DSP56166 to DSP56167
4-32
• The SSI TDE and TUE bits can be incorrectly set after being cleared if the clear
• The PLL may lock at the maximum VCO frequency during power up at low
• The PLL Lock bit failed to be asserted properly in an over-damped system.
• The PLL may lock at the maximum VCO frequency when coming out of Stop
• Due to SXFC external filter capacitor leakage and noise, the PLL frequency
operation is performed is performed during the last half bit period of the
current word, or during the first half bit period of the next word.
voltage and high temperature. (The recommended workaround was to
connect the SXFC to GND and not V
(The recommended workaround was to use a software time loop of at least 5
ms instead of the “lock bit” polling loop.)
mode of operation. (The workaround was to connect a 10 M resistor
between SXFC and GND.)
may jitter by as much as 25 MHz at the PLL input frequency rate (output from
the ID divider). (The workaround was to use a faster reference clock, a smaller
Multiplication Factor, a low-leakage capacitor for the SXFC loop filter
capacitor, and to reduce the coupled noise level into the PLL by careful board
design.)
DSP56167/D, Rev. 1
CC
).
MOTOROLA

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