dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 106

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Design Considerations
Special Design Considerations for Conversions from DSP56166 to DSP56167
4-30
EXTERNAL PROGRAM MEMORY ACCESS DISABLE
External Program Memory Access Disable Programming Environment:
External Program Memory Access Disable Operation
Where:
BH
BS
BGPD
EPABDIS External PAB Disable; preset to 0 during processor reset
X
P
*
BH BS BGPDEPABDIS *
15 14
For those users that run strictly from internal program memory, it is now possible
to disable the external program memory access as a power-saving measure.
Note: This has no effect on external data memory or external peripheral
When this feature is enabled, the internal path from the PAB bus to the Port A
address pins is disabled, eliminating unnecessary switching inside the DSP.
A new control bit called External PAB Disable (EPABDIS) has been added to the
Bus Control Register, BCR[12] at X:$FFDE, to disable the external program
memory access.
EPABDIS is preset to 0 during processor reset. So, coming out of reset the Port A
bus functions exactly as the DSP56166. When EPABDIS is set to 1 via software
programming, Port A access is restricted to external data memory or external
peripheral accesses.
Note: Attempts to access external program memory while this bit is set result in
If EPABDIS is cleared to 0 via software programming, then Port A functionality
will revert back to be the same as when the chip just came out of reset. However,
due to pipeline delays inside the DSP, there should be at least 1 instruction cycle
between when EPABDIS is cleared and external program memory is accessed.
Figure 4-19 Port A Bus Control Register (BCR), X:$FFDE
accesses.
Bus Request Hold; preset to 0 during processor reset
Bus State Status; Read Only
Bus Grant Pull-Down; preset to 0 during processor reset
External Data Memory Wait States; preset to 1 during processor reset
External Program Memory Wait States; preset to 1 during processor reset
reserved bits; write 0 for future compatibility
an incorrect address appearing at the Port A address pins. The results of
the operation will be incorrect.
13
12
11 10
DSP56167/D, Rev. 1
* X4 X3
9
8
X2 X1
7
6
5
X0 P4
4
P3
3
2
P2 P1 P0
1
MOTOROLA
0