dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 107

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Feature Changes Description
DSP56166 Chip Errata Fixed in the DSP56167
MOTOROLA
Changes to DSP56166 functionality in the DSP56167 include:
Refer to the section titled Analog I/O Considerations on page 4-4 for a detailed
description of design requirements for the on-chip codec.
The following DSP56166 chip errata (some of which required hardware
workarounds) have been fixed in the DSP56167:
• Codec input circuitry can be single-ended or differential
• Codec input impedance is software selectable
• Codec output reference voltages (VRDA and VRAD) are now 1/2 V
• Codec output drive capability (for VRDA, VRAD, SPKP, and SPKM) is now
• Codec single-ended small signal output (SPKP and SPKM) impedance has
• Codec DAC outputs (absolute single-ended) now can swing between 0.35 V
• CHKAAU instruction does not operate correctly if there is a killed instruction
• The second read from internal data memory of a dual read instruction will
• The OnCE NOS0 status flag does not get updated correctly when the DSP
• The SSI RS/TX interrupt occurs when the interrupt is enabled even though
• The SSI receiver does not operate independently from the transmitter in
• In External Gated Clock mode, the SSI STD signal can remain tri-stated during
• In External Gated Clock mode, the STD signal should not be tri-stated until
0.35 mA
changed to a range of 4.0–16.0
Hz
and V
between the last valid AALU update and CHKAAU
transfer the wrong data if it is preceded by a conditional transfer instruction
with the condition being false (i.e., the transfer is aborted).
enters the Wait or Stop mode of operation.
the RE and TE bits are cleared (i.e., function disabled).
Gated Clock mode.
the first two bits of the transmitted word.
the end of the transmitted word regardless when the TE bit is cleared (i.e., the
function is disabled).
Special Design Considerations for Conversions from DSP56166 to DSP56167
DD
– 0.4 V.
DSP56167/D, Rev. 1
for 300 Hz and a range of 12.6–50.4
Design Considerations
DDA
for 3000
4-31