dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 33

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

PHASE LOCK LOOP (PLL) AND OTHER CLOCK TIMING
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
V
WS = number of wait states programmed into the external bus access using BCR (WS = 0–15)
MOTOROLA
DD
Num
10
11
12
13
14
15
16
17
18
19
PLL output frequency
EXTAL input clock amplitude
Note:
= 5.0 V 10%; T
RESET Assertion to Address, Data and control signals
High Impedance
Minimum Stabilization Duration
Asynchronous RESET Deassertion to First External
Address Output
Synchronous Reset Setup Time from RESET Deassertion
to Rising Edge of CLKO
Synchronous Reset Delay Time from CLKO High to the
First External Access
Mode Select Setup Time
Mode Select Hold Time
Edge-Triggered Interrupt Request Width
Delay from IRQA, IRQB, IRQC Assertion to External Data
Memory Access Out Valid
— Caused by First Interrupt Instruction Fetch
— Caused by First Interrupt Instruction Execution
Delay from IRQA, IRQB, IRQC Assertion to General
Purpose Output Valid Caused by the Execution of the
First Interrupt Instruction
1.
2.
OMR Bit 6 = 0
OMR Bit 6 = 1
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (60 MHz)
Maximum DSP operating frequency
An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level
range (V
Characteristics
J
= –40 to +115˚C; C
ILC
7
Table 2-6 PLL and Other Clock Characteristics
> 0.2 V
7
Characteristics
DD
or V
DSP56167/D, Rev. 1
1
IHC
L
< 0.7 V
= 50 pF + 2 TTL loads
DD
Phase Lock Loop (PLL) and Other Clock Timing
).
Min
10
1
16T + 3
11T + 3
19T + 3
22T + 3
600KT
Min
Maximum f
60T
16T
4.8
4.0
8.0
—
5
Max
V
DD
1
18T + 15
16T + 16
cyc – 2
Max
21.0
—
—
—
—
—
—
—
—
Specifications
MHz
Unit
V
P
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-7