adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 32

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 29. Serial Ports—Enable and Three-State
1
Table 30. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
1
1
1
1
1
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or
External Receive FS with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
DAI_P20 - 1
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
DAI_P20 - 1
DAI_P20 - 1
(SCLK)
(SCLK)
(FS)
(FS)
DRIVE
DRIVE
t
DDTLFSE
t
DDTLFSE
Figure 22. External Late Frame Sync
Rev. D | Page 32 of 56 | April 2008
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
t
SFSE/I
SFSE/I
t
LATE EXTERNAL TRANSMIT FS
DDTENFS
t
DDTENFS
SAMPLE
SAMPLE
1ST BIT
DATA CHANNEL
1ST BIT
t
HDTE/I
t
HDTE/I
Min
2
–1
Min
0.5
DRIVE
DRIVE
t
A/B) ARE ROUTED TO THE DAI_P20-1 PINS
HFSE/I
t
HFSE/I
K and B Grade
K and B Grade
1
t
DDTE/I
t
DDTE/I
Max
7
Max
9
2ND BIT
2ND BIT
8.5
Max
Max
10.5
Y Grade
Y Grade
Unit
ns
ns
ns
Unit
ns
ns