adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 21
adsp-21364bbc
Manufacturer Part Number
adsp-21364bbc
Description
Sharc Processor
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-21364BBC.pdf
(56 pages)
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Part Number:
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Reset
Table 15. Reset
1
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 16. Interrupts
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
Parameter
Timing Requirement
t
WRST
SRST
V
IPW
DD
1
and CLKIN (not including start-up time of external clock oscillator).
IRQx Pulse Width
RESET Pulse Width Low
RESET Setup Before CLKIN Low
RESET
CLKIN
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
FLAG2
DAI20
(IRQ2 - 0)
-
Rev. D | Page 21 of 56 | April 2008
-
1
0
Figure 11. Interrupts
Figure 10. Reset
t
WRST
t
IPW
Min
4t
8
t
SRST
CK
Min
2 × t
PCLK
+2
Unit
ns
ns
Unit
ns
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