adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 28

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 24. 16-Bit Memory Read Cycle
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
This parameter is only available when in EMPP = 0 mode.
DRS
DRH
ALEW
ADAS
ALERW
RRH
RWALE
RDDRV
ADAH
ALEHZ
RW
PCLK
2
1
1
= (peripheral) clock period = 2 × t
1
PCLK
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0)
AD15–0 Data Setup Before RD High
AD15–0 Data Hold After RD High
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted
ALE Deasserted to Read Asserted
Delay Between RD Rising Edge to Next Falling
Edge
Read Deasserted to ALE Asserted
ALE Address Drive After Read High
AD15–0 Address Hold After ALE Deasserted
ALE Deasserted to Address/Data15–0 in High-Z t
RD Pulse Width
AD15 - 0
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP
WHEN EMPP = 0, MULTIPLE
SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.
ALE
WR
RD
CCLK
t
t
ADAS
VALID ADDRESS
ALEW
RD
Figure 19. Read Cycle for 16-Bit Memory Timing
PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
t
ADAH
Rev. D | Page 28 of 56 | April 2008
t
ALEHZ
t
ALERW
0, ONLY ONE
t
t
DRS
VALID DATA
RW
Min
3.3
0
2 × t
t
2 × t
H + t
F + H + 0.5
F + H + t
t
D – 2.0
PCLK
PCLK
PCLK
PCLK
– 2.3
PCLK
PCLK
PCLK
– 2.5
RD
t
DRH
– 2.0
– 3.8
K and B Grade
– 1.4
PCLK
t
PULSE OCCURS BETWEEN ALE CYCLES.
RRH
– 2.3
VALID DATA
Max
t
PCLK
t
RWALE
+ 3.0
t
RDDRV
Min
4.5
0
2 × t
t
2 × t
H + t
F + H + 0.5
F + H + t
t
t
D – 2.0
PCLK
PCLK
PCLK
ADDRESS
– 2.5
– 2.3
PCLK
PCLK
PCLK
VALID
– 2.0
– 3.8
– 1.4
PCLK
Y Grade
– 2.3
Max
t
PCLK
+ 3.8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns