adsp-21364bbc Analog Devices, Inc., adsp-21364bbc Datasheet - Page 17

• Manufacturer Part Number: adsp-21364bbc
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

PACKAGE INFORMATION
The information presented in
the package branding for the ADSP-2136x processor. For a
complete listing of product availability, see
Page
Table 9. Package Brand Information
ESD CAUTION
MAXIMUM POWER DISSIPATION
See Estimating Power for the ADSP-21362 SHARC Processors
(EE-277) for detailed thermal and power information regarding
maximum power dissipation. For information on package ther-
mal specifications, see
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
#
yyww
53.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Figure 5. Typical Package Brand
Thermal Characteristics on Page
#yyww country_of_origin
S
a
vvvvvv.x n.n
ADSP-2136x
Field Description
Temperature Range
Package Type
RoHS Compliant Option (optional)
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliant Designation
Date Code
tppZ-cc
Figure 5
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 10
provides details about
Ordering Guide on
may cause perma-
Rev. D | Page 17 of 56 | April 2008
46.
Table 10. Absolute Maximum Ratings
TIMING SPECIFICATIONS
The ADSP-2136x’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLK_CFG1–0 pins
(see
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the
serial ports).
The ADSP-2136x’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock (the
clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in
and
In
where:
f
PLLM = Multiplier value programmed
PLLN = Divider value programmed.
Table 11. ADSP-2136x Clock Generation Operation
Note the definitions of various clock periods shown in
which are a function of CLKIN and the appropriate ratio con-
trol shown in
Parameter
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature Under Bias
CCLK
Timing
Requirements
CLKIN
CCLK
Table
Table
Table 8 on Page
f
CCLK
= CCLK frequency
11, CCLK is defined as:
12.
= (2 × PLLM × f
Table
11.
15). To determine switching frequencies
Description
Input Clock
Core Clock
INPUT
VDD
DDEXT
) ÷ (2 × PLLN)
DDINT
)
)
)
Calculation
1/t
1/t
Rating
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
–0.5 V to +3.8 V
–0.5 V to V
200 pF
–65°C to +150°C
125°C
CK
CCLK
DDEXT
Table 11
Table 12
+ 0.5 V