mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 82

• Manufacturer Part Number: mt46v128m4bn
• Description: 512mb X4, X8, X16 Ddr Sdram
• Manufacturer: Micron Semiconductor Products

POWER-DOWN (CKE Not Active)
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command, until completion of the
access. Thus a clock suspend is not supported. For READs, an access completion is
defined when the read postamble is satisfied; for WRITEs, when the write recovery time
(
Power-down, as shown in Figure 55, is entered when CKE is registered LOW and all
criteria in Table 30 on page 40 are met. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when a row is
active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CK, CK#, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down mode. Exiting power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. However, power-down duration is limited by the refresh requirements of
the device (
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
t
WR) is satisfied.
t
REFC).
82
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512Mb: x4, x8, x16 DDR SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Operations