mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 49

• Manufacturer Part Number: mt46v128m4bn
• Description: 512mb X4, X8, X16 Ddr Sdram
• Manufacturer: Micron Semiconductor Products

CAS Latency (CL)
Figure 24:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
CAS Latency
Note:
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 24. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 32 on page 50 indi-
cates the operating frequencies at which each CL setting can be used.
COMMAND
COMMAND
COMMAND
BL = 4 in the cases shown; shown with nominal
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
T0
T0
T0
CL = 2
CL = 2.5
CL = 3
49
NOP
NOP
NOP
T1
T1
T1
TRANSITIONING DATA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
T2
NOP
NOP
NOP
T2
512Mb: x4, x8, x16 DDR SDRAM
t
AC,
T2n
T2n
t
DQSCK, and
T3
T3
NOP
NOP
NOP
T3
DON’T CARE
©2000 Micron Technology, Inc. All rights reserved.
T3n
T3n
T3n
t
DQSQ.
Operations