mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 62

• Manufacturer Part Number: mt46v128m4bn
• Description: 512mb X4, X8, X16 Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 35:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
x4, x8 Data Output Timing –
Notes:
DQ (first data no longer valid)
1.
2.
3. DQs transitioning after DQS transition define the
4. For a x4, only two DQs apply.
5.
6. The data valid window is derived for each DQS transitions and is defined as
DQ (first data no longer valid)
All DQ and DQS, collectively 6
t
t
transition, and ends with the last valid DQ transition.
T2n are an “early DQS”; at T3, a “nominal DQS”; and at T3n, a “late DQS”.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
DQ (last data valid)
DQ (last data valid)
Earliest signal transition
Latest signal transition
DQS 3
CK#
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK
t
t
DQSQ,
CL or
t
HP:
T1
t
t
QH =
CH clock transition collectively when a bank is active.
t HP
t
62
QH, and Data Valid Window
1
t
HP -
t HP
t
QHS.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSQ
t QH 5
T2
2
window
Data
valid
T2
T2
T2
t HP
512Mb: x4, x8, x16 DDR SDRAM
1
t
DQSQ window. DQS transitions at T2 and
t DQSQ
T2n
t QH 5
2
window
t HP
T2n
T2n
Data
valid
T2n
1
T3
t DQSQ
t QH 5
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t HP
2
window
1
Data
valid
T3
T3
T3
T3n
t DQSQ
t QH 5
Operations
t HP
t
QH -
1
2
window
T4
T3n
T3n
Data
valid
T3n
t
DQSQ.