mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 60

• Manufacturer Part Number: mt46v128m4bn
• Description: 512mb X4, X8, X16 Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 33:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
READ-to-PRECHARGE
Notes:
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
DQS
DQS
DQS
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
t
RAS (MIN) is met.
CL = 2
t
AC,
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
DQSCK, and
CL = 3
60
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
PRE
T2
PRE
PRE
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
DO
n
T2n
T2n
512Mb: x4, x8, x16 DDR SDRAM
DO
n
T3
NOP
NOP
NOP
T3
T3
DON’T CARE
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
t
RC (MIN) is met.
©2000 Micron Technology, Inc. All rights reserved.
T4
T4
T4
NOP
NOP
NOP
TRANSITIONING DATA
T4n
Operations
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
Row
Row
ACT
ACT
ACT