mt46v128m4bn Micron Semiconductor Products, mt46v128m4bn Datasheet - Page 53

• Manufacturer Part Number: mt46v128m4bn
• Description: 512mb X4, X8, X16 Ddr Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. L; Core DDR Rev. A 4/07 EN
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 31 on page 58. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 32 on page 59. The
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defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 33 on page 60. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both
and
last data elements.
DQSS (MAX) case has a longer bus idle time. (
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RP have been met. Part of the row precharge time is hidden during the access of the
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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512Mb: x4, x8, x16 DDR SDRAM
DQSS [MIN] and
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DQSS (NOM) case is shown; the
©2000 Micron Technology, Inc. All rights reserved.
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DQSS [MAX] are
Operations
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RAS