cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 98

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

ISA Bus Interface Pins
SA<11:0> - System Address Bus, Inputs
SA<15:12> - Upper System Address Bus, Inputs
SD<7:0> - System Data Bus, Bi-directional, 24mA drive
AEN - Address Enable, Input
IOR - Read Command Strobe, Input
IOW - Write Command Strobe, Input
IOCHRDY - I/O Channel Ready, Open Drain Output, 8mA drive
DRQ<A,B,C> - DMA Requests, Outputs, 24mA drive
98
These signals are decoded during I/O cycles to determine access to the various functional
blocks within the part as defined by the configuration data written during a Plug and Play
configuration sequence.
These signals are multi-function pins, shared with the CDROM and modem interface, that
default to the upper address bits SA12 through SA15. These pins are generally used for
motherboard designs that want to eliminate address decode aliasing. Using these pins as upper
address bits forces the part to only accept valid address decodes when A12-A15 = 0. If these
pins are not used for address decodes (or for CDROM support), they should be tied to SGND.
These signals are used to transfer data to and from the part and associated peripheral devices.
Reads from peripheral devices can be disabled (the part does not drive the SD<7:0> pins) by
setting the SDD bit in the Hardware Configuration data. Reads from peripheral devices are
automatically disabled whenever the XD pins are used as serial port pins (SPS/SPE or WTEN
set to one).
This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal
is low during an I/O cycle and high during a DMA cycle.
This active low signal defines a read cycle to the part. The cycle may be a register read or a
read from the part’s DMA registers.
This active low signal indicates a write cycle to the part. The cycle may be a write to a control
register or a DMA register.
This signal is driven low by the part during ISA bus cycles in which the part is not able to
respond within a minimum cycle time. IOCHRDY is forced low to extend the current bus
cycle. The bus cycle is extended until IOCHRDY is brought high.
These active high outputs are generated when the part is requesting a DMA transfer. This
signal remains high until all the bytes have been transferred as defined by the current transfer
data type. The DRQ<A,B,C> outputs must be connected to 8-bit DMA channel request signals
only. The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3.
The defaults can be changed by modifying the Hardware Resource data. Note that DRQA is a
5 Volt-only pin. When the ISA bus is run at 3.3 Volts, DRQA can either be used with the proper
level translator, or DRQA can be left unconnected and not used.
CS4237B
DS213PP4