cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 13
cs4237b
Manufacturer Part Number
cs4237b
Description
Crystalclear Advanced Audio System With 3d Sound
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS4237B.pdf
(114 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
cs4237b-JQ
Manufacturer:
CRYSTAL
Quantity:
246
Company:
Part Number:
cs4237b-KQ
Manufacturer:
CRYSTAL
Quantity:
9
Company:
Part Number:
cs4237b-KQ
Manufacturer:
CRYSTAL
Quantity:
346
Company:
Part Number:
cs4237b-KQ
Manufacturer:
CRYSTAL
Quantity:
329
Part Number:
cs4237b-KQ
Manufacturer:
CRYSTAL
Quantity:
20 000
Logical Device 5 supports a modem connected
to the peripheral port. This interface, on the ex-
ternal peripheral port, supports modems with 2
to 256 I/O locations (only SA2-SA0 are buffered
through the part) and supports a base address
and an interrupt. Although this logical device is
listed as a modem, any external device that fits
within the resources listed above may be substi-
tuted.
ISA Bus Interface
The 8-bit parallel I/O and 8-bit parallel DMA
ports provide an interface which is compatible
with the Industry Standard Architecture (ISA)
bus. The ISA Interface enables the host to com-
DS213PP4
Logical Device 0
WSS Codec:
Synthesis:
I/O: WSSbase
2 DMA Chan.
1 Interrupt
I/O: SBbase
(DMA shared)
(Interrupt shared)
I/O: SYNbase
[1 Interrupt]
SBPro:
Logical Device 1
Game Port:
I/O: GAMEbase
Logical Device 2
I/O: CTRLbase
[1 Interrupt]
Control:
Figure 1. Logical Devices
PnP ISA Bus
Interface
Logical Device 3
municate with the various functional blocks
within the part via two types of accesses: Pro-
grammed I/O (PIO) access, and DMA access.
A number of configuration registers must be pro-
grammed prior to any accesses by the host
computer. The configuration registers are pro-
grammed via a Plug-and-Play configuration
sequence or via configuration software provided
by Crystal Semiconductor.
I/O CYCLES
Every device that is enabled, requires I/O space.
An I/O cycle begins when the part decodes a
valid address on the bus while the DMA ac-
knowledge signals are inactive and AEN is low.
The IOR and IOW signals determine the direc-
tion of the data transfer. For read cycles, the part
will drive data on the SD<7:0> lines while the
host asserts the IOR strobe. Write cycles require
the host to assert data on the SD<7:0> lines and
strobe the IOW signal. Data is latched on the ris-
ing edge of the IOW strobe.
I/O: MPUbase
1 Interrupt
MPU-401:
Logical Device 4
I/O:
[1 Interrupt]
[1 DMA Chan.]
CDROM:
CDbase
ACDbase
Logical Device 5
I/O: COMbase
[1 Interrupt]
Modem:
CS4237B
13