cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 44

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

RLBM
RLIM
RLOM
When IFM=1 and FMRM=1, FM remapping is en-
abled. When WTEN=1 and WTRMD=0, Wavetable
remapping is enabled. If either synthesizer remap is
enabled, right LINE analog volume is controlled
through X1. With remapping the bit definitions are:
RR7-RR0
Timer Lower Base (I20)
Default = 00000000
TL7-TL0
44
(Synthesis)
TL7
D7
RLINE
TL6
D6
+12 to -34.5 dB
D5
TL5
Right LINE Bypass Mute. In MODE 3,
when set to 1, the analog Right Line
Input, RLINE, (bypassing the gain
block) to the input mixer is muted.
In MODEs 1 & 2, this bit is not avail-
able and is internally controlled by
RSS1,0 in I1.
Right LINE Input Mute. In MODE 3,
when set to 1, the Right Line Input,
RLINE, from the volume control to
the input mixer is muted.
In MODEs 1 & 2, this bit is not avail-
able and internally forced on (muted).
Right LINE Output Mute.
When set to 1, the Right Line Input,
RLINE, from the volume control to
the output mixer is muted.
Right Remapped Register.
When IFM=1 and FMRM=1, writes
to I19 will write the Internal FM regis-
ter X7.
When WTEN=1 and WTRMD=0,
writes to I19 will write the Wavetable
synthesis register X17.
Lower Timer Bits: This is the low order
byte of the 16-bit timer base register.
Writes to this register cause both
timer base registers to be loaded
RLG4-G0
TL4
D4
TL3
D3
RLOM
RLBM
RLIM
TL2
D2
TL1
D1
To Output
To Input
Mixer
Mixer
TL0
D0
Timer Upper Base (I21)
Default = 00000000
TU7-TU0
Alternate Sample Frequency Select (I22)
Default = 00000000
CS2
DIV5 - DIV0
SRE
TU7
D7
D7
DIV5
TU6
D6
D6
DIV4
TU5
D5
D5
into the internal timer; therefore, the
upper timer register should be
loaded before the lower. Once the
count reaches zero, an interrupt is
generated, if enabled, and the timer
is automatically reloaded with these
base registers.
Upper Timer Bits: This is the high
order byte of the 16-bit timer. The
time base is determined by the fre-
quency base selected from either
C2SL in I8 or CS2 in I22.
C2SL = 0 - 24.576MHz / 245
(9.969 s)
C2SL = 1 - 16.9344MHz / 168
(9.92 s)
Clock 2 Base Select. This bit selects
the base clock frequency used for
generating the audio sample rate.
Note that the part uses only one
crystal to generate both clock base
frequencies. This bit can be disabled
by setting IFSE in X11.
0 - 24.576 MHz base
1 - 16.9344 MHz base
Clock Divider. These bits select the
audio sample frequency for both cap-
ture and playback. These bits can
be overridden by IFSE in X11.
Fs = (2*XT)/(M*N)
DIV3
TU4
D4
D4
DIV2
TU3
D3
D3
DIV1
TU2
D2
D2
CS4237B
DIV0
TU1
D1
D1
DS213PP4
CS2
TU0
D0
D0