cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 45

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

SRE
Extended Register Access (I23)
Default = 00000xx0
ACF
res
XA4
XRAE
DS213PP4
XA3
D7
XA2
D6
XA1
D5
XT = 24.576 MHz
XT = 16.9344 MHz CS2 = 1
N = DIV5-DIV0
16
12
(M set by OSM1,0 in I10)
M = 64 for Fs > 24 kHz
M = 128 for 12 kHz < Fs
M = 256 for Fs
Alternate Sample Rate Enable. When
this bit is set to a one, bits 0-3 of I8
will be ignored, and the sample fre-
quency is then determined by CS2,
DIV5-DIV0, and the oversampling
mode bits OSM1, OSM0 in I10. Note
that this register can be overridden
(disabled) by IFSE in X11.
ADPCM Capture Freeze. When set,
the capture ADPCM accumulator
and step size are frozen. This bit
must be set to zero for adaptation to
continue. This bit is used when
pausing a ADPCM capture stream.
Reserved. Must write 0. Could read
as 0 or 1.
Extended Register Address bit 4.
Along with XA3-XA0, enables ac-
cess to extended registers X16,
X17, and X25. MODE 3 only.
Extended Register Access Enable.
Setting this bit converts this register
from the extended address register
to the extended data register. To con-
vert back to an address register, R0
must be written. MODE 3 only.
XA0
D4
N
N
49 for XT = 24.576 MHz
33 for XT = 16.9344 MHz
XRAE
D3
12 kHz
XA4
D2
CS2 = 0
D1
res
24 kHz
ACF
D0
XA3-XA0
Alternate Feature Status (I24)
Default = x0000000
PU
PO
CO
CU
PI
CI
TI
D7
res
D6
TI
D5
CI
with XA4, sets the register number
(X0-X17+X25) accessed when
XRAE is set. MODE 3 only. See the
WSS Extended Register section for
more details.
Playback Underrun: When set,
indicates the DAC has run out of
data and a sample has been missed.
Playback Overrun: When set,
indicates that the host attempted to
write data into a full FIFO and the
data was discarded.
Capture Overrun: When set,
indicates that the ADC had a sample
to load into the FIFO but the FIFO
was full. In this case, this bit is set
and the new sample is discarded.
Capture Underrun: Indicates the host
has read more data out of the FIFO
than it contained. In this condition,
the bit is set and the last valid byte
is read by the host.
Playback Interrupt: Indicates an
interrupt is pending from the play-
back DMA count registers.
Capture Interrupt: Indicates an
interrupt is pending from the capture
DMA count registers.
Timer Interrupt: Indicates an interrupt
is pending from the timer registers
Extended Register Address. Along
D4
PI
D3
CU
D2
CO
CS4237B
D1
PO
D0
PU
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