EMD56324P Emlsi Inc., EMD56324P Datasheet - Page 3

• Manufacturer Part Number: EMD56324P
• Description: 256m 8m X 32 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

Table 2: Pad Description
CK, CKB
CKE
CSB
RASB, CASB,
WEB
DM0~DM3
BA0, BA1
A0 ~ A11
DQ0~DQ31
DQS0~DQS3
VDD
Symbol
Supply Power Supply
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
Clock : CK and CKB are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced
to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived from CK/
CKB.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is
synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.
Input buffers, excluding CK, CKB and CKE, are disabled during power-down and self refresh mode
which are contrived for low standby power consumption.
Chip Select : CSB enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CSB is registered HIGH. CSB provides for external bank selection on
systems with multiple banks. CSB is considered part of the command code.
Command Inputs: CASB, RASB, and WEB(along with CSB) define the command being entered.
DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ
and DQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-
mand.
Data Bus: Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
center-aligned with write data. Used to capture write data. For x32 device, DQS0 corresponds
to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 corresponds
to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
3
Descriptions
256M: 8M x 32 Mobile DDR SDRAM
EMD56324P
.
Preliminary
Rev 0.0