EMD56324P Emlsi Inc., EMD56324P Datasheet - Page 2

• Manufacturer Part Number: EMD56324P
• Description: 256m 8m X 32 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

256M : 8M x 32bit Mobile DDR SDRAM
FEATURES
Table 1: ORDERING INFORMATION
NOTE :
1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
· 1.8V power supply, 1.8V I/O power
· LVCMOS compatible with multiplexed address.
· Double-data-rate architecture; two data transfers per clock
· Bidirectional data strobe(DQS)
· Four banks operation.
· MRS cycle with address key programs.
· Differential clock inputs(CK and CKB).
· EMRS cycle with address key programs.
· Internal auto TCSR
· Deep power-down(DPD) mode.
· DM for write masking only.
· Auto refresh and self refresh modes.
· 64㎳ refresh period (4K cycle).
· Operating temperature range (-25℃ ~ 85℃).
Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
cycle
(Temperature Compensated Self Refresh)
· PASR(Partial Array Self Refresh).
· DS (Driver Strength)
· CAS latency (2, & 3).
· Burst length (2, 4, 8, & 16).
· Burst type (Sequential & Interleave).
EMD56324P-60(DDR332)
EMD56324P-75(DDR266)
Part No.
166㎒(CL3), 83㎒(CL2)
133㎒(CL3), 83㎒(CL2)
Max Freq.
2
GENERAL DESCRIPTION
rate Dynamic RAM. Each 67,108,854 bits bank is organized as
4,096 rows by 512columns by 32 bits, fabricated with EMLSI’s
high performance CMOS technology.
speed operation. The double data rate architecture is essentially
a 2n-prefetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O balls.
and programmable latencies allow the same device to be useful
for a variety of high bandwidth and high performance memory
system applications.
This EMD56324P is 268,435,456 bits synchronous double data
This device uses a double data rate architecture to achieve high-
Range of operating frequencies, programmable burst lengths
Interface
LVCMOS
256M: 8M x 32 Mobile DDR SDRAM
Wafer Biz.
Package
EMD56324P
Preliminary
Remark
Rev 0.0