S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 44

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

9.15
44
QUAD Page Program (QPP)
The Quad Page Program instruction is similar to the Page Program instruction, except that the Quad Page
Program (QPP) instruction allows up to 256 bytes of data to be programmed at previously erased (FFh)
memory locations using four pins: IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#), instead of just one
pin (SI) as in the case of the Page Program (PP) instruction. This effectively increases the data transfer rate
by up to four times, as compared to the Page Program (PP) instruction. The QPP feature can improve
performance for PROM Programmer and applications that have slow clock speeds < 5 MHz. Systems with
faster clock speed will not realize much benefit for the QPP instruction since the inherent page program time
is much greater than the time it take to clock-in the data.
To use QPP, the Quad Enable Bit in the Configuration Register must be set (QUAD = 1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL = 1). The instruction is initiated by driving the CS# pin low then shifting the instruction code
“32h” followed by a 24 bit address (A23-A0) and at least one data byte, into the IO pins. The CS# pin must be
held low for the entire length of the instruction while data is being sent to the device. All other functions of
Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown
below.
W#/ACC/IO2
W#/ACC/IO2
HOLD#/IO3
HOLD#/IO3
SO/IO1
SO/IO1
SI/IO0
SI/IO0
SCK
SCK
CS#
CS#
6
5
4
7
*
Byte 5
40
0
1
2
3
0
41
Figure 9.18 QUAD Page Program Instruction Sequence
1
6
4
5
Byte 6
7
*
42
2
1
2
3
0
43
D a t a
Instruction
3
6
Byte 7
4
5
44
7
*
4
45
0
1
2
3
5
S25FL129P
6
5
4
Byte 8
46
7
*
S h e e t
6
1
2
3
47
0
7
6
5
4
Byte 9
7
*
48
23
*
8
2
3
0
1
49
22
9
( P r e l i m i n a r y )
Byte 10
6
4
5
7
*
50
21
10
Address
1
2
3
24 Bit
0
51
Byte 11
3
6
5
4
28
52
7
*
2
1
2
3
29
0
53
Byte 12
6
1
4
5
30
54
7
*
0
31
0
1
2
3
55
S25FL129P_00_04 November 2, 2009
6
4
5
32
7
*
Byte 1
Byte 253
6
4
5
7
*
0
1
2
3
33
0
1
2
3
Byte 2
34
4
5
6
7
*
Byte 254
6
4
5
7
*
35
0
1
2
3
1
2
3
0
Byte 3
36
4
5
6
7
*
Byte 255
6
4
5
7
*
37
0
1
2
3
1
2
3
0
38
Byte 4
4
5
6
7
*
Byte 256
6
5
4
7
*
39
0
1
2
3
1
2
3
0
*MSB