S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 3

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

Distinctive Characteristics
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
Architectural Advantages
S25FL129P
128-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet (Preliminary)
Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
Memory architecture
– Uniform 64 KB sectors
– Uniform 256 KB sectors (no 4-KB sub-sectors)
– 256-byte page size
– Backward compatible with the S25FL128P (uniform 256 KB sector)
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64 KB & 256 KB sectors
– Sub-sector erase (P4E) command (20h) for 4 KB sectors
– Sub-sector erase (P8E) command (40h) for 8 KB sectors
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
device
(for uniform 64-KB sector device only)
(for uniform 64-KB sector device only)
compatibility
– Top or bottom parameter block (Two 64-KB sectors broken
down into sixteen 4-KB sub-sectors each)
Publication Number S25FL129P_00
Revision 04
Performance Characteristics
Memory Protection Features
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory
or by the customer
CFI (Common Flash Interface) compliant: allows host system
to identify and accommodate multiple flash devices
Process technology
– Manufactured on 0.09 µm MirrorBit
Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-contact WSON package (6 x 8 mm)
– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration
– 24-ball BGA (6 x 8 mm) package, 6 x 4 pin configuration
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
– QUAD I/O FAST_READ: 80 MHz clock rate or
Power saving standby mode
– Standby Mode 80 µA (typical)
– Deep Power-Down Mode 3 µA (typical)
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits to
– Status Register Block Protection bits (BP2, BP1, BP0) in status
20 MB/s effective data rate
40 MB/s effective data rate
protect specified memory areas
Issue Date November 2, 2009
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process technology