S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 41

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

9.13
November 2, 2009 S25FL129P_00_04
Write Registers (WRR)
The Write Registers (WRR) command allows changing the bits in the Status and Configuration Registers. A
Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is
required prior to writing the WRR command.
The host system must drive CS# low, then write the WRR command and the appropriate data byte on SI
Figure
The WRR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be
used for that purpose.
The Status Register consists of one data byte in length; similarly, the Configuration Register is also one data
byte in length. The CS# pin must be driven to the logic low state during the entire duration of the sequence.
The WRR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W#/ACC pin together place the device in the Hardware Protected Mode (HPM). The device ignores all
WRR commands once it enters the Hardware Protected Mode (HPM).
driven low and the SRWD bit must be 1 for this to occur.
The Write Registers (WRR) instruction has no effect on the P/E Error and the WIP bits of the Status &
Configuration Registers. Any bit reserved for the future is always read as a ‘0’
The CS# chip select input pin must be driven to the logic high state after the eighth (see
sixteenth (see
executed. If CS# is driven high after the eighth cycle then only the Status Register is written to; otherwise,
after the sixteenth cycle both the Status and Configuration Registers are written to. As soon as the CS# chip
select input pin is driven to the logic high state, the self-timed Write Registers cycle is initiated. While the
Write Registers cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is a ‘1’ during the self-timed Write Registers cycle, and is
a ‘0’ when it is completed. When the Write Registers cycle is completed, the Write Enable Latch (WEL) is set
to a ‘0’. The WRR command can operate at a maximum clock frequency of 104 MHz.
SCK
CS#
SO
SI
9.15.
D a t a
Figure
Figure 9.15 Write Registers (WRR) Instruction Sequence – 8 data bits
9.16) bit of data has been latched in. If not, the Write Registers (WRR) instruction is not
S h e e t
0
1
2
High Impedance
( P r e l i m i n a r y )
n I
t s
3
S25FL129P
u r
t c
4
o i
Table 9.8
n
5
6
shows the status register bits and their functions.
7
MSB
7
8
6
9
5
S
Table 9.9
1
a t
0
u t
s
4
11
R
e
i g
3
t s
12
shows that W#/ACC must be
r e
n I
2
13
1
Figure
14
0
15
9.15) or
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