S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 30

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

9.5
30
DUAL I/O High Performance Read Mode (DIOR)
The Dual I/O High Performance Read instruction is similar to the Dual Output Read instruction, except that it
improves throughput by allowing input of the address bits (A23-A0) using 2 bits per SCK via two input pins
(SI/IO2 and SO/IO1), at a maximum frequency of 80 MHz.
The host system must first select the device by driving CS# low. The Dual I/O High Performance Read
command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with two
bits latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out
two bits at a time through IO0 (SI) and IO1 (SO).
The DUAL I/O High Performance Read command sequence is shown in
on page
automatically increments to the next higher address after each byte of data is output. The entire memory
array can therefore be read with a single DUAL I/O High Performance Read command. When the highest
address is reached, the address counter reverts to 00000h, allowing the read sequence to continue
indefinitely.
In addition, address jumps can be done without exiting the Dual I/O High Performance Mode through the
setting of the Mode bits (after the Address (A23-0) sequence, as shown in
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble
(bits 7-4) of the Mode bits control the length of the next Dual I/O High Performance instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON’T
CARE (“x”). If the Mode bits equal Axh, then the device remains in Dual I/O High Performance Read Mode
and the next address can be entered (after CS# is raised high and then asserted low) without requiring the
BBh instruction opcode, as shown in
However, if the Mode bits are any value other than Axh, then the next instruction (after CS# is raised high and
then asserted low) requires the instruction sequence, which is normal operation. The following sequences will
release the device from Dual I/O High Performance Read mode; after which, the device can accept standard
SPI instructions:
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be
driven high at any time during data output to terminate a read operation.
SO/IO1
SI/IO0
CS#
SCK
1. During the Dual I/O High Performance Instruction Sequence, if the Mode bits are any value other
2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and
than Axh, then the next time CS# is raised high and then asserted low, the device will be released
from Dual I/O High Performance Read mode.
data input (IO0 & IO1) are not set for a valid instruction sequence, then the device will be released
from Dual I/O High Performance Read mode.
25. The first address byte specified can start at any location of the memory array. The device
0
Hi-Z
Figure 9.5 DUAL I/O High Performance Read Instruction Sequence
1
2
Instruction
3
4
D a t a
5
6
Figure
7
S25FL129P
22
23
8
*
S h e e t
20
21
9.6, thus eliminating eight cycles for the instruction sequence.
9
Address
24 Bit
10
2
3
18 19 20 21 22 23 24 25 26 27
( P r e l i m i n a r y )
0
1
6
7
*
4
5
Mode Bits
2
3
0
1
6
7
*
4
Byte 1
5
Figure 9.5
S25FL129P_00_04 November 2, 2009
IO0 & IO1 Switches from Input to Output
Figure
2
3
0
1
7
*
6
9.5). This added feature
28 29 30 31
and
Byte 2
4
5
2
3
Table 9.1
0
1
6
7
*
*MSB