S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 40

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

9.12
40
SCK
CS#
SO
SI
Read Configuration Register (RCR)
Parameter Sector Erase (P4E, P8E), Sector Erase (SE), Quad Page Programming (QPP) and Bulk Erase
(BE) instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed.
The Bulk Erase (BE) instruction can be executed only when the Block Protection (BP2, BP1, BP0) bits are set
to 0’s.
The default condition of the BP2-0 bits is binary 000 (all 0’s).
Erase Error bit (E_ERR): The Erase Error Bit is used as a Erase operation success and failure check. When
the Erase Error bit is set to a “1”, it indicates that there was an error which occurred in the last erase
operation. With the Erase Error bit set to a “1”, this bit is reset with the Clear Status Register (CLSR)
command.
Program Error bit (P_ERR): The Program Error Bit is used as a Program operation success and failure
check. When the Program Error bit is set to a “1”, it indicates that there was an error which occurred in the last
program operation. With the Program Error bit set to a “1”, this bit is reset with the Clear Status Register
(CLSR) command.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (W#/ACC) signal. The Status Register Write Disable (SRWD) bit is operated in conjunction with the
Write Protect (W#/ACC) input pin. The Status Register Write Disable (SRWD) bit and the Write Protect (W#/
ACC) signal allow the device to be put in the Hardware Protected mode. With the Status Register Write
Disable (SRWD) bit set to a “1” and the W#/ACC driven to the logic low state, the device enters the Hardware
Protected mode; the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) and the nonvolatile bits
of the Configuration Register (TBPARM, TBPROT, BPNV and QUAD) become read-only bits and the Write
Registers (WRR) instruction opcode is no longer accepted for execution.
Note that the P_ERR and E_ERR bits will not be set to a 1 if the application writes to a protected memory
area.
The Read Configuration Register (RCR) instruction opcode allows the Configuration Register contents to be
read out of the SO serial output pin. The Configuration Register contents may be read at any time, even while
a program, erase, or write cycle is in progress. When one of these cycles is in progress, it is recommended to
the user to check the Write In Progress (WIP) bit of the Status Register before issuing a new instruction
opcode to the device. The Configuration Register originally shows 00h when the device is first shipped from
the factory to the customer. (Refer to
details.)
0
Figure 9.14 Read Configuration Register (RCR) Instruction Sequence
1
High Impedance
2
n I
t s
3
u r
t c
4
o i
n
5
6
D a t a
7
MSB
7
8
Section 7.8 on page
S25FL129P
6
9
Configuration Register Out
S h e e t
5
1
0
4
11
3
12
( P r e l i m i n a r y )
2
13
15,
1
14
Table 7.1
0
15
MSB
7
16
Configuration Register Out
6
17
and
S25FL129P_00_04 November 2, 2009
5
18
Table 7.1 on page 16
4
19
3
20
21
2
22
1
23
0
MSB
7
for more