SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 39

• Manufacturer Part Number: SB16C1058-TQFP128
• Description: Octal-uart Controller With 256-byte Fifo
• Manufacturer: IK Semicon Co., Ltd

7.7 Modem Control Register (MCR, Page 0)
MCR controls the interface with the modem, data set, or peripheral device that is
emulating the modem. Table 14 shows MCR bit settings.
Table 14:
Bit
7
6
5
4
3
2
1
0
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
Modem Control Register Description
Description
Clock Prescaler Select.
Page 2 Select/Xoff Re-Transmit Access Enable
Xon Any Enable.
Internal Loop Back Enable.
OUT2/Interrupt Output Enable.
OUT1/Xoff Re-transmit Enable.
NRTS Output.
NDTR Output.
OCTAL UART WITH 256-BYTE FIFO
0 : Divide by 1 clock input (default).
1 : Divide by 4 clock input.
0 : Enable access to page 0 register when LCR[7] is ‘0’ (default).
1 : Enable access to page 2 register and Xoff re-transmit bit
0 : Disable Xon any (default).
1 : Enable Xon any.
0 : Disable loop back mode (default).
1 : Enable internal loop back mode. In this mode the MCR[3:0]
0 : INTx outputs disabled (default). During loop back mode,
1 : INTx outputs enabled. During loop back mode, OUT2 output
OUT2 is not available as an output pin on the IN16C1058.
0 : Xoff re-transmit disable when MCR[6] is ‘0’. During loop
1 : Xoff re-transmit enable when MCR[6] is ‘1’. During loop back
OUT1 is not available as an output pin on the IN16C1058.
Xoff re-transmit is operated with XRCR, refer to XRCR.
0 : Force NRTS output to ‘1’. During loop back mode, controls
1 : Force NRTS output to ‘0’. During loop back mode, controls
0 : Force NDTR output to ‘1’. During loop back mode, controls
1 : Force NDTR output to ‘0’. During loop back mode, controls
when LCR[7] is ‘0’.
signals are looped back into MSR[7:4] and TXD output is
looped back to RXD input internally.
OUT2 output ‘0’ and it controls MSR[7] to ‘1’.
‘1’ and it controls MSR[7] to ‘0’.
back mode, OUT1 output to ‘0’ and it controls MSR[6] to ‘1’.
mode, OUT1 output to ‘1’ and it controls MSR[6] to ‘0’.
MSR[4] to ‘1’.
MSR[4] to ‘0’.
MSR[5] to ‘1’.
MSR[5] to ‘0’.
IN16C1058
JUNE 2009
REV 1.0
39