SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 36

• Manufacturer Part Number: SB16C1058-TQFP128
• Description: Octal-uart Controller With 256-byte Fifo
• Manufacturer: IK Semicon Co., Ltd

IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
36
Table 11:
Bit
7
6
Table 11:
Bit
5:0
00
00
00
00
00
00
01
10
_
_
_
_
_
_
_
_
0001
0110
0100
1100
0010
0000
0000
0000
Symbol
ISR[7]
ISR[6]
Interrupt Priority List and Reset Functions
Priority
―
1
2
2
3
4
5
6
Interrupt Status Register Description
Interrupt Status Register Description…continued
REV 1.0
Description
FCR[0]/256 TX FIFO Empty.
FCR[0]/256 RX FIFO Full.
7.4 Interrupt Status Register (ISR, Page 0)
Interrupt Type
None
Receiver Line Status
Receive Data Available
Character Timeout Indi-
cation
Transmit Holding
Register Empty
Modem Status
Receive Xoff or Special
Character
NRTS, NCTS Status
during Auto RTS/CTS
flow control
When 256-byte FIFO mode is disabled (default).
When 256-byte FIFO mode is enabled.
When 256-byte FIFO mode is disabled (default).
When 256-byte FIFO mode is enabled.
empty bit is ‘1’, it means TX FIFO is empty and if ‘0’, it means 256 bytes character is fully
stored in TX FIFO.
empty bit is ‘1’, it means 256 bytes character is fully stored in RX FIFO and if ‘0’, it means
RX FIFO is empty.
Mirror the content of FCR[0].
0 : 256-byte TX FIFO is full.
1 : 256-byte TX FIFO is not full.
When TCR is ‘00h’, there are two situations of TX FIFO full and TX FIFO empty. If 256 TX
Mirror the content of FCR[0].
0 : 256-byte RX FIFO is not full.
1 : 256-byte RX FIFO is full.
When RCR is ‘00h’, there are two situations of RX FIFO full and RX FIFO empty. If 256 RX
The UART provides multiple levels of prioritized interrupts to minimize software work load.
ISR provides the source of interrupt in a prioritized manner.
Table 11 shows ISR[7:0] bit settings.
Interrupt Source
None
OE, PE, FE, BI
Receiver data available, reaches
trigger level.
At least one data is in RX FIFO and
there are no more data in FIFO during
four character time.
When THR is empty or TCR passes
above trigger level (FIFO enable).
NCTS, NDSR, NDCD, NRI
Detection of a Xoff or special character.
NRTS pin or NCTS pin change state
from ‘0’ to ‘1’.
Interrupt Reset Control
―
Reading the LSR.
Reading the RBR or RCR
falls below trigger level.
Reading the RBR.
Reading the ISR or write
data on THR.
Reading the MSR.
Reading the ISR.
Reading the ISR.