SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 24

• Manufacturer Part Number: SB16C1058-TQFP128
• Description: Octal-uart Controller With 256-byte Fifo
• Manufacturer: IK Semicon Co., Ltd

IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
24
REV 1.0
6.6 Interrupts
As there are eight independent channel UARTs in IN16C1058, so there are eight internal
interrupts. Interrupts are assigned internal interrupts: INT0, INT1, INT2, INT3, INT4, INT5,
INT6 and INT7 for each channel. Each interrupt has six prioritized level’s interrupt
generation capability. The IER enables each of the six types of interrupts and INT signal
in response to an interrupt generation. When an interrupt is generated, the ISR indicates
that an interrupt is pending and provides the type of interrupt. And IN16C1058 can handle
for eight interrupts with one global interrupt. Global interrupt treats eight of each interrupt
as one interrupt, so it is useful when external system has few interrupt resource. GICR
determines whether global interrupt occurs or not. While GICR[x] is set to ‘1’, an interrupt
that is generated in one of eight channel UARTs and treated as UNMASK is transmitted to
GINT. But if GICR[x] is cleared to ‘0’, an interrupt is not transmitted to GINT though
interrupts are generated in one of eight channel UARTs and treated as MASK. So this
interrupt is not transmitted to external CPU. GISR is the status of each channel UART. It
just show the status of eight channels whether interrupt is generated or not. If GISR[0] is
cleared to ‘0’, it means that interrupt is not generated in the UART and if set to ‘1’, it
means that interrupt is generated. The value of GISR[0] shows the status of interrupt
generated in the UART.
Each internal interrupt is decided by the value of ‘GICR x GISR’. In other words, when the
both of them have logic ‘1’, internal interrupt of the channel is generated. And the global
interrupt is decided by logic AND for each internal interrupt. If one of eight internal
interrupt is generated, the global interrupt is generated.