SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 33

• Manufacturer Part Number: SB16C1058-TQFP128
• Description: Octal-uart Controller With 256-byte Fifo
• Manufacturer: IK Semicon Co., Ltd

Table 9:
A[2:0]
Addr.
0h
0h
1h
2h
2h
3h
4h
5h
6h
7h
0h
1h
1h
2h
5h
6h
7h
GICR
GISR
MCR
Reg.
MSR
RCR
THR
RBR
FCR
SCR
DLM
TCR
LCR
LSR
FSR
DLL
IER
ISR
Internal Registers Description
RX FIFO
Interrupt
Interrupt
Interrupt
0/NCTS
FCR[0]/
256-TX
Enable
Trigger
Enable
Divisor
Empty
(MSB)
NDCD
Select
Status
Clock
Bit 15
Level
Mask
FIFO
Error
CH 7
Bit 7
Data
Bit 7
Bit 7
Bit 7
Bit 7
CH7
Bit 7
Bit 7
RX
0
Re-Transmit
Select/Xoff
TX Brake
Interrupt
Interrupt
Interrupt
0/NRTS
FCR[0]/
256-RX
Enable
Trigger
Page 2
Access
Enable
THR &
Empty
Status
(LSB)
Bit 14
Level
Mask
FIFO
CH 6
Bit 6
Bit 6
Bit 6
Bit 6
TSR
Bit 6
CH6
Bit 6
Bit 6
NRI
Full
Set
RX
0
Interrupt
Interrupt
Interrupt
Interrupt
Trigger
TX HW
Control
Enable
Priority
(MSB)
Empty
NDSR
Status
Status
0/Xoff
Parity
0/Xon
Bit 13
Level
Mask
CH 5
Bit 5
0/TX
THR
Flow
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
CH5
Bit 5
Bit 5
Any
Set
Page 0 Registers
Page 1 Registers
Page 2 Registers
OCTAL UART WITH 256-BYTE FIFO
Interrupt
Interrupt
Interrupt
Receive
0/Sleep
Enable
Priority
Trigger
TX SW
Control
0/Loop
Select
Status
Status
NCTS
Mode
(LSB)
Parity
Break
Bit 12
Level
Mask
CH 4
Bit 4
Type
Back
0/TX
Flow
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
CH4
Bit 4
Bit 4
Interrupt
Interrupt
Framing
∆
Interrupt
Interrupt
Modem
Enable
Priority
Enable
Enable
OUT2/
Status
Select
Status
Parity
Mode
Bit 11
Mask
DMA
Error
CH 3
Bit 3
INTx
NDCD
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
CH3
Bit 3
Bit 3
0
TX FIFO
Transmit
Interrupt
Interrupt
Xoff Re-
Interrupt
Interrupt
Receive
Enable
Priority
Enable
OUT1/
Status
Status
Reset
Parity
Bit 10
∆
Mask
Error
CH 2
Bit 2
Bit 2
Bit 2
Bit 2
Stop
Bit 2
Bit 2
CH2
Bit 2
Bit 2
Line
Bits
NRI
0
IN16C1058
JUNE 2009
Interrupt
Interrupt
Interrupt
Interrupt
Overrun
∆
RX HW
Control
Enable
Priority
Length
Empty
Status
Status
NRTS
Reset
FIFO
Word
Mask
CH 1
Bit 1
Error
THR
NDSR
Flow
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 9
CH1
Bit 1
Bit 1
RX
Available
Interrupt
Interrupt
Interrupt
Interrupt
Receive
Receive
REV 1.0
∆
RX SW
Control
Enable
Priority
Enable
Length
Ready
NDTR
Status
Status
FIFO
Word
Mask
CH 0
Bit 0
Data
Data
Flow
Bit 0
Bit 0
Bit 0
Bit 0
NCTS
Bit 0
Bit 0
Bit 8
CH0
Bit 0
Bit 0
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