ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 98

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Output Frequency of OC2 (OFREQ2[3:0]). This field specifies the frequency of output clock OC2.
The frequencies of the T0 APLL and the T4 APLL are configured in the
and Digital2 frequencies are configured in the
controlled by the value of the OCR5.AOF2 bit.
AOF2 = 0: (standard decodes)
AOF2 = 1: (alternate decodes)
Bits 3 to 0: Output Frequency of OC1 (OFREQ1[3:0]). This field specifies the frequency of output clock OC1.
The frequencies of the T0 APLL and T4 APLL are configured in the
Digital2 frequencies are configured in the
by the value of the OCR5.AOF1 bit.
AOF1 = 0: (standard decodes)
Rev: 012108
____________________________________________________________________________________________ DS3102
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see
0100 = Digital1 (see
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
0000 = Output disabled (i.e., low)
0001 = T0 APLL frequency divided by 64
0010 = T4 APLL frequency divided by 20
0011 = T4 APLL frequency divided by 12
0100 = T4 APLL frequency divided by 10
0101 = T4 APLL frequency divided by 5
0110 = T4 APLL frequency divided by 2
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see
0100 = Digital1 (see
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
7
1
Table
Table
Table
Table
OFREQ2[3:0]
6
0
OCR1
Output Configuration Register 1
60h
7-9)
7-8)
7-9)
7-8)
MCR7
5
0
MCR7
register. See Section 7.8.2.3. The decode of this field is controlled
register. See Section 7.8.2.3. The decode of this field is
4
0
T0CR1
0
3
T0CR1
and
and
T4CR1
2
1
OFREQ1[3:0]
T4CR1
registers. The Digital1 and
registers. The Digital1
1
0
98 of 141
0
1