ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 77

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Lock T4 to T0 (LKT4T0). When this bit is set to 1 (and T0CR1:T4APT0 = 0) all output clocks are generated
from the T0 DPLL, and the T4CR1:T4FREQ field selects the frequency of the T4 APLL. See Section 7.8.2.2. When
LKT4T0 = 0, the T4 APLL can be locked to either the T4 DPLL or the T0 DPLL, depending on the setting of
T0CR1:T4APT0.
Bits 3 to 0: T4 DPL Force Selected Reference (T4FORCE[3:0]). This field provides a way to force a specified
input clock to be the selected reference for the T4 DPLL. Internally this is accomplished by forcing the clock to have
the highest priority (as specified in PTAB1:REF1). Since the T4 DPLL always operates in revertive mode, the
forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well.
When a reference is forced, the activity monitor and frequency monitor for that input continue to operate and affect
the relevant ISR,
not allowed to switch to another input clock. See Section 7.6.3.
Rev: 012108
____________________________________________________________________________________________ DS3102
0 = T4 APLL can lock to either T4 or the T0 DPLL.
1 = T4 APLL always locked to the T0 DPLL.
0000 = Automatic source selection (normal operation)
0001 = Force to IC1
0010 = Force to IC2
0011 = Force to IC3
0100 = Force to IC4
0101 = Force to IC5
0110 = Force to IC6
0111 = {unused value}
1000 = Force to IC8
1001 = Force to IC9
1010–1110 = {unused value}
1111 = Automatic source selection (normal operation)
LKT4T0
VALSR
7
0
and
—
MSR
6
0
MCR4
Master Configuration Register 4
35h
register bits. However, when the reference is declared invalid, the T4 DPLL is
—
5
0
—
4
0
0
3
T4FORCE[3:0]
2
0
1
0
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0
0