ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 11

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

5.
5.1
5.2
5.3
Rev: 012108
____________________________________________________________________________________________ DS3102
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Detailed Features
Input Clock Features
Eight input clocks: four CMOS/TTL (≤ 125MHz) and four LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz)
CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz
LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to
155.52MHz plus 156.25MHz
All input clocks are constantly monitored by programmable frequency monitors and activity monitors
Fast activity monitor can disqualify the selected reference after two missing clock cycles
Three optional 2/4/8kHz frame-sync inputs
T0 DPLL Features
High-resolution DPLL plus two or three low-jitter output APLLs
Sophisticated state machine automatically transitions between free-run, locked, and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.5mHz to 400Hz
Separately configurable acquisition bandwidth and locked bandwidth
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency, early/late, and multicycle
Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
Multicycle phase detection and locking (up to ±8191UI) improves jitter tolerance and lock time
Phase build-out in response to reference switching
Less than 5 ns output clock phase transient during phase build-out
Output phase adjustment up to ±200ns in 6ps steps with respect to selected input reference
High-resolution frequency and phase measurement
Holdover frequency averaging over 8- or 110-minute intervals
Fast detection of input clock failure and transition to holdover mode
Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
T4 DPLL Features
High-resolution DPLL plus low-jitter output APLL
Programmable bandwidth from 18Hz to 70Hz
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency, early/late, and multicycle
Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
Multicycle phase detection and locking (up to ±8191UI) improves jitter tolerance and lock time
2kHz and 8kHz frame syncs with programmable polarity and pulse width
Can operate independently or locked to T0 DPLL
Phase detector can be used to measure phase difference between two input clocks
Optional PLL bypass mode provides input clock monitoring, selection, and optional frequency division but
bypasses the DPLL and APLL when they are not needed (e.g., dividing an input clock to 8kHz)
High-resolution frequency and phase measurement
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