ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 121

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Phase Offset Recalibration (RECAL). When set to 1, this configuration bit causes a recalibration of the
phase offset between the output clocks and the selected reference. This process puts the DPLL into mini holdover,
internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the
OFFSET
the RECAL process causes no change in the phase offset of the output clocks. RECAL is automatically reset to 0
when recalibration is complete. See Section 7.7.8.
Bits 6 to 4: Sync Monitor Limit (MONLIM[2:0]). This field configures the sync monitor limit. When the external
frame-sync input is misaligned with respect to the MFSYNC output by the specified number of resampling clock
cycles, a frame-sync monitor alarm is declared in the FSMON bit of the
Bits 3 to 0: External Frame-Sync Reference Source (SOURCE[3:0]). When external frame sync is configured
for SYNC1 automatic mode, this field specifies the input clock to associate with the SYNC1 pin. See Section
7.9.2.1.
Rev: 012108
____________________________________________________________________________________________ DS3102
0 = Normal operation
1 = Phase offset recalibration
000 = ± 1UI
001 = ± 2UI
010 = ± 3UI
011 = ± 4UI
100 = ± 5UI
101 = ± 6UI
110 = ± 7UI
111 = ± 8UI
0000 = IC1
0010 = IC2
0011 = IC3
0100 = IC4
0101 = IC5
0110 = IC6
0111 = {unused value, undefined}
1000 = IC8
1001 = IC9
1010–1011 = {unused values, undefined}
11XX = SYNC123 mode
registers, and then switches the DPLL out of mini holdover. Unlike simply writing the
RECAL
7
0
6
0
FSCR3
Frame-Sync Configuration Register 3
7Ch
MONLIM[2:0]
5
1
4
0
3
1
OPSTATE
2
SOURCE[3:0]
0
register. See Section 7.9.2.6.
1
1
OFFSET
121 of 141
registers,
0
1