ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 107

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: T4 DPLL Bandwidth (T4BW[2:0]). See Section 7.7.3.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: T0 DPLL Locked Bandwidth (T0LBW[4:0]). This field configures the bandwidth of the T0 DPLL when
locked to an input clock. When AUTOBW = 0 in the
and for locked operation. When AUTOBW = 1,
is used for locked operation. See Section 7.7.3.
Rev: 012108
____________________________________________________________________________________________ DS3102
00 = 18Hz
01 = 35Hz
10 = 70Hz
11 = {unused value, undefined}
00000 = 0.5mHz
00001 = 1mHz
00010 = 2mHz
00011 = 4mHz
00100 = 8mHz
00101 = 15mHz
00110 = 30mHz
00111 = 60mHz
01000 = 0.1Hz
01001 = 0.3Hz
01010 = 0.6Hz
01011 = 1.2Hz
01100 = 2.5Hz
01101 = 4Hz (default)
01110 = 8Hz
01111 = 18Hz
10000 = 35Hz
10001 = 70Hz
10010 = 120Hz
10011 = 250Hz
10100 = 400Hz
10101–11111 = unused
—
7
0
0
7
0
—
6
0
0
6
0
T4BW
T4 Bandwidth Register
66h
T0LBW
T0 DPLL Locked Bandwidth Register
67h
—
5
0
0
5
0
T0ABW
MCR9
0
4
0
4
0
bandwidth is used for acquisition while T0LBW bandwidth
register, the T0LBW bandwidth is used for acquisition
3
0
0
1
3
T0LBW[4:0]
2
0
0
2
1
1
0
1
0
T4BW[1:0]
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0
0
0
1