ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 9

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

____________________________________________________________________________________________ DS3102
4.
Detailed Description
Figure 3-1
illustrates the blocks described in this section and how they relate to one another. Section
5
provides a
detailed feature list.
The DS3102 is a highly integrated timing card IC for systems with SONET/SDH or Synchronous Ethernet ports. At
1
the core of this device are two digital phase-locked loops (DPLLs) labeled T0 and T4
. DPLL technology makes
use of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to implement PLLs that are
precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process
variations. The DS3102’s DPLLs are digitally configurable for input and output frequencies, loop bandwidth,
damping factor, pull-in/hold-in range, and a variety of other factors. Both DPLLs can directly lock to many common
telecom frequencies and also can lock at 8kHz to any multiple of 8kHz up to 156.25MHz. The DPLLs can also
tolerate and filter significant amounts of jitter and wander.
The T0 DPLL is responsible for generating the system clocks used to time the outgoing traffic interfaces of the
system (SONET/SDH, Synchronous Ethernet, etc.). To perform this role in a variety of systems with diverse
performance requirements, the T0 DPLL has a sophisticated feature set and is highly configurable. T0 can
automatically transition among free-run, locked, and holdover states without software intervention. In free-run, T0
generates a stable, low-noise clock with the same frequency accuracy as the external oscillator connected to the
REFCLK pin. With software calibration the DS3102 can even improve the accuracy to within ±0.02ppm. When an
input reference has been validated, T0 transitions to the locked state in which its output clock accuracy is equal to
the accuracy of the input reference. While in the locked state, T0 acquires a high-accuracy long-term average
frequency value to use as the holdover frequency. When its selected reference fails, T0 can very quickly detect the
failure and enter the holdover state to avoid affecting its output clock. From holdover it can automatically switch to
the next highest priority input reference, again without affecting its output clock (hitless switching). Switching
among input references can be either revertive or nonrevertive. When all input references are lost, T0 stays in
holdover, in which it generates a stable low-noise clock with initial frequency accuracy equal to its stored holdover
value and drift performance determined by the quality of the external oscillator. With a suitable local oscillator the
T0 DPLL provides holdover performance suitable for all applications up to and including Stratum 3E. T0 can also
perform phase build-outs and fine-granularity output clock phase adjustments.
The T4 DPLL has a much less demanding role to play and therefore is much simpler than T0. Often T4 is used as
a frequency converter to create a derived DS1- or E1-rate clock (frequency locked to an incoming SONET/SDH
port) to be sent to a nearby BITS Timing Signal Generator (TSG, Telcordia terminology) or Synchronization Supply
Unit (SSU, ITU-T terminology). In other applications T4 is phase-locked to T0 and used as a frequency converter to
produce additional output clock rates for use within the system, such as N x DS1, N x E1, N x DS2, DS3, E3,
125MHz for Synchronous Gigabit Ethernet, or 156.25MHz for Synchronous 10G Ethernet. T4 can also be
configured as a measuring tool to measure the frequency of an input reference or the phase difference between
two input references.
At the front end of both the T0 and T4 DPLLs is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This
block continuously monitors as many as 8 different input clocks of various frequencies for activity and frequency
accuracy. In addition, ICSDM maintains separate input clock priority tables for the T0 and T4 DPLLs, and can
automatically select and provide the highest priority valid clock to each DPLL without any software intervention.
The ICSDM block can also divide the selected clock down to a lower rate as needed by the DPLL.
The Output Clock Synthesizer and Selector (OCSS) block shown in
Figure 3-1
and in more detail in
Figure 7-1
contains three output APLLs—T0 APLL, T0 APLL2, and T4 APLL—and their associated DFS engines and output
divider logic plus several additional DFS engines. The APLL DFS blocks perform frequency translation, creating
clocks of other frequencies that are phase/frequency locked to the output clock of the associated DPLL. The APLLs
multiply the clock rates from the APLL DFS blocks and simultaneously attenuate jitter. Altogether the output blocks
of the DS3102 can produce more than 90 different output frequencies including common SONET/SDH, PDH and
Synchronous Ethernet rates plus 2kHz and 8kHz frame-sync pulses.
1
These names are adapted from output ports of the SETS function specified in ITU-T and ETSI standards such as ETSI EN 300 462-2-1.
Rev: 012108
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